imec Advances Ferroelectric Memory for AI Systems

Artificial-intelligence workloads are straining memory systems as models demand greater capacity, bandwidth and energy efficiency at sustainable cost. Conventional DRAM and SRAM are becoming harder to scale, prompting Belgium-based semiconductor research hub imec to investigate ferroelectric memory. The technology could combine low-voltage operation with denser three-dimensional integration, offering a potential route around the memory bottlenecks confronting data-intensive AI and next-generation computing architectures.

On June 17, 2026, imec unveiled two advances at the IEEE/JSAP Symposium on VLSI Technology & Circuits. Its scaled ferroelectric capacitor operated at about 1.3 volts while maintaining remnant polarization above 40 μC/cm² and endurance of at least 10¹³ cycles, specifications relevant to DRAM-like memory. Separately, imec reported the first functional five-word-line vertical stack of IGZO-based ferroelectric field-effect transistor, or FeFET, memory cells, using a dual-gate design with a back gate to improve erase efficiency.