Intel, Cadence Expand AI-Driven Chip Design Partnership for 14A

Electronic design automation is critical at advanced nodes because chipmakers must align circuit layouts with increasingly complex transistor and power-delivery features before tapeout. Cadence and Intel Foundry expanded their relationship on June 8, 2026, under a multiyear Design Technology Co-Optimization agreement starting with Intel 14A. The pact combines Cadence’s agentic AI-driven EDA tools and Design IP with Intel’s process expertise to improve power, performance and area and shorten development cycles for AI, high-performance computing and mobile chips. Financial terms were not disclosed.

Cadence said on July 27, 2026, that its AI-driven digital and custom reference flows had been certified for Intel 18A-P and Intel 14A using the foundry’s latest process design kits. The signoff-ready portfolio covers synthesis, place-and-route, timing and power signoff, physical and reliability verification, and analog/custom design. The companies also co-developed a packaging flow for Intel’s EMIB and EMIB-T technologies, while Cadence interface and memory IP test chips were validated in Intel 18A silicon, reducing adoption risk for advanced SoCs.