AMD Unveils EPYC Venice to Challenge NVIDIA Vera

As demand for artificial intelligence and cloud computing surges, server-chip performance and power efficiency have become critical battlegrounds for technology giants. AMD has long competed with Intel in the x86 server market and relies heavily on leading foundry TSMC's advanced manufacturing processes. The chip upgrade marks a new milestone in their advanced-process partnership and is set to redefine technical standards in high-performance computing and AI acceleration.

AMD said it will formally unveil its first Zen 6-based EPYC Venice server processor at its Advancing AI event in July 2026. It is the world's first server chip manufactured on TSMC's 2-nanometer process and features up to 256 computing cores. The processor is aimed squarely at the x86 and AI-accelerated computing markets, underscoring AMD and TSMC's lead in next-generation semiconductor technology.

AMD’s EPYC Venice is a next-generation server processor based on the Zen 6 architecture and designed for data centers, high-performance computing and large-scale cloud deployments. It will feature separate mainstream and high-core-count CCD designs and use TSMC’s 2-nanometer process. The product is critical to AMD’s efforts to expand its server market share and compete with Intel and Nvidia platforms.

AMD announced in April 2025 that the first Venice chips had completed tape-out. The processors are expected to launch in 2026 and will be among the first high-performance computing products to use TSMC’s N2 process, while some compute dies could subsequently adopt N2P. AMD also plans to use higher core density and energy efficiency to compete with Nvidia’s Vera Rubin platform, which is scheduled for release in 2026.