Google Adopts Intel EMIB Packaging for TPU Chips

Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, has emerged as a competitive alternative to Taiwan Semiconductor Manufacturing Co.’s CoWoS packaging for custom artificial-intelligence chips. Reports that Intel secured orders from Apple and Google have raised the stakes for TSMC, whose advanced-process leadership is increasingly tied to packaging capacity. Tight CoWoS supply and architectural constraints are prompting major technology customers to consider additional routes for connecting high-performance computing dies and memory.

TSMC is secretly developing an EMIB-like packaging technology with IC substrate maker Kinsus Interconnect Technology, according to the latest report, in a defensive push to retain custom AI processor business. The project is intended to ease CoWoS capacity and design limitations as Intel presses its advantage with Apple and Google. As of July 31, 2026, neither company had formally confirmed the collaboration, and no investment amount, production timetable, official technology name or committed customer orders had been disclosed.

As demand for artificial intelligence computing surges, advanced packaging has become a key battleground in determining the performance of high-end AI chips. TSMC has long dominated the foundry market for the vast majority of high-end AI chips with its leading CoWoS packaging technology. Seeking to break that monopoly, semiconductor giant Intel is investing aggressively in advanced packaging. It views the field as a core weapon in its bid to challenge TSMC’s foundry dominance and win orders from major international customers.

Intel formally unveiled its next-generation EMIB-T advanced packaging technology at an IEEE technical conference. The technology incorporates through-silicon vias to improve vertical scaling and power delivery, aiming to meet the demanding requirements of high-performance AI chips and HBM4E memory. Intel plans to further expand the packaging scale in 2028, directly challenging TSMC’s CoWoS technology as it seeks to pull ahead in advanced packaging.

The expansion of AI clusters is pushing copper interconnects against bandwidth, power and thermal limits, making co-packaged optics (CPO), which places optical engines close to compute chips, increasingly critical. A single defect can render a package worth tens of thousands of dollars unusable. Intel's EMIB uses localized silicon bridges to reduce costs and thermal coupling, challenging the scale and ecosystem advantages of TSMC's CoWoS.

TechNews summarized the social-media debate on June 18, 2026. Supporters estimated that Intel could capture 90% of the co-packaged silicon photonics market within five years. Critics noted that TSMC's CoWoS-S supports a 5.5-reticle-size package and 12 HBM stacks in 2026, rising to 9.5 reticle sizes and 16 HBM stacks in 2027, and that NVIDIA has already adopted its COUPE technology. The outcome will still depend on yield and mass-production capabilities.

Rising AI chip performance is driving a surge in demand for multi-die integration and high-bandwidth memory, leaving TSMC’s CoWoS capacity chronically constrained. Intel’s EMIB technology connects dies through embedded silicon bridges. If Intel can achieve stable mass production, EMIB could become an important option for Google and NVIDIA to diversify advanced-packaging supply risks, while supporting Intel Foundry’s turnaround strategy.

The latest market reports in July 2026 said Intel’s EMIB packaging yield had reached 90% and that the company was investing billions of dollars to expand capacity and capture orders spilling over from TSMC’s CoWoS operations. Analyst Ming-Chi Kuo said Google had previously evaluated placing chip orders directly. Market reports also suggest Google and NVIDIA could adopt EMIB for their next-generation AI chips, but the customers, order values and mass-production schedules have yet to be officially confirmed.

Generative AI and high-performance computing are driving demand for larger chips, greater power capacity and faster data transfer, putting cost and yield pressure on conventional large silicon interposers. Intel Foundry’s EMIB technology connects chiplets such as CPUs, GPUs and HBM through embedded silicon bridges. EMIB-T adds vertical power delivery using through-silicon vias, shortening current paths and making the technology key to improving the performance of large AI accelerators while controlling costs.

Details emerged on May 28, 2026, and Intel showcased its progress at ECTC 2026. Interconnect bump pitch has been reduced to 25 micrometers, while packages can measure up to 120×120 millimeters and integrate compute and memory dies spanning more than nine reticle sizes. The technology supports HBM4e at more than 12 Gb/s and UCIe at 64 Gb/s. Intel did not disclose its investment, customers or a mass-production timetable.

AI server chips must integrate compute dies, HBM and multiple other components, making advanced packaging a key area of semiconductor competition. After becoming a TSMC CoWoS partner, Powerchip Semiconductor Manufacturing Corp. (PSMC) has also entered Intel's EMIB supply chain. The move shows its business expanding beyond mature-node foundry services into the high-end packaging market.

PSMC recently became an Intel EMIB advanced-packaging partner and is also pursuing HBM-related business with Micron. Chairman Frank Huang said the company expects AI server demand to drive growth in specialty processes and plans to position itself in the market through 3D wafer stacking and integrated passive-device technologies. The partnership timetable, investment amount and mass-production scale have not been disclosed.