Mark RadarMARK RADAR
About
EN
Sign in

Intel's EMIB Challenges TSMC's CoWoS in Race for AI Optical Interconnect and CPO Edge

2 reports · First detected 2026-06-08 · Last active 2026-06-18

The expansion of AI clusters is pushing copper interconnects against bandwidth, power and thermal limits, making co-packaged optics (CPO), which places optical engines close to compute chips, increasingly critical. A single defect can render a package worth tens of thousands of dollars unusable. Intel's EMIB uses localized silicon bridges to reduce costs and thermal coupling, challenging the scale and ecosystem advantages of TSMC's CoWoS.

TechNews summarized the social-media debate on June 18, 2026. Supporters estimated that Intel could capture 90% of the co-packaged silicon photonics market within five years. Critics noted that TSMC's CoWoS-S supports a 5.5-reticle-size package and 12 HBM stacks in 2026, rising to 9.5 reticle sizes and 16 HBM stacks in 2027, and that NVIDIA has already adopted its COUPE technology. The outcome will still depend on yield and mass-production capabilities.

All Coverage

2 original reports

The Backstory

The history behind this event
Google Adopts Intel EMIB Packaging for TPU Chips2026-08-27 · 1 reports · similarity 0.82

Advanced packaging has become a strategic bottleneck in artificial intelligence hardware as chipmakers seek to combine large compute dies with high-bandwidth memory. TSMC’s CoWoS technology dominates the market, but tight capacity has pushed cloud providers developing in-house accelerators to qualify alternative suppliers. Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, is emerging as a credible option for complex AI chips and a potential challenger to TSMC’s packaging franchise.

Google has adopted Intel’s EMIB advanced-packaging technology for its Tensor Processing Unit chips after the process passed yield validation, according to the latest supply-chain report. The qualification could strengthen Intel’s position among cloud companies designing proprietary AI accelerators. MediaTek, an ASIC design partner for Google, is also accelerating a diversified packaging strategy as CoWoS capacity remains constrained, giving EMIB a chance to capture additional production demand.

Intel Targets 2027 Production for Lower-Cost EMIB-T Packaging2026-08-04 · 1 reports · similarity 0.81

Advanced packaging, which connects compute dies with high-bandwidth memory, has become a critical constraint on the performance and supply of artificial-intelligence accelerators. Intel is positioning EMIB-T as a key part of its effort to expand its foundry and packaging businesses in a market led by Taiwan Semiconductor Manufacturing Co. With TSMC’s CoWoS capacity remaining tight, a viable alternative could give chip designers more flexibility on costs, delivery schedules and supply-chain diversification.

Intel’s EMIB-T packaging yield has approached 90%, while its cost is about half that of TSMC’s CoWoS solution, according to the latest report. The company plans to begin mass production in 2027, targeting AI chip customers that are particularly sensitive to packaging expenses. If Intel can preserve those yield and cost advantages at commercial scale, EMIB-T could strengthen its bid for external orders and offer a more credible challenge to TSMC’s position in advanced packaging.

Intel Unveils EMIB-T Advanced Packaging Technology to Challenge TSMC2026-07-11 · 1 reports · similarity 0.83

As demand for artificial intelligence computing surges, advanced packaging has become a key battleground in determining the performance of high-end AI chips. TSMC has long dominated the foundry market for the vast majority of high-end AI chips with its leading CoWoS packaging technology. Seeking to break that monopoly, semiconductor giant Intel is investing aggressively in advanced packaging. It views the field as a core weapon in its bid to challenge TSMC’s foundry dominance and win orders from major international customers.

Intel formally unveiled its next-generation EMIB-T advanced packaging technology at an IEEE technical conference. The technology incorporates through-silicon vias to improve vertical scaling and power delivery, aiming to meet the demanding requirements of high-performance AI chips and HBM4E memory. Intel plans to further expand the packaging scale in 2028, directly challenging TSMC’s CoWoS technology as it seeks to pull ahead in advanced packaging.

Mark Radar|MARK RADAR

If you search news on Google, you can set Mark Radar as a preferred source—our coverage will show up more often in your results. Set as preferred source on Google →

All times are in Taipei time (GMT+8)