TSMC Develops Next-Generation CoPoS Packaging to Ease AI Chip Capacity Bottleneck

Demand for generative AI and high-performance computing is pushing chipmakers beyond the size limits of individual dies, increasing reliance on advanced packaging. TSMC’s CoWoS technology combines processors and high-bandwidth memory in a single package, making it central to AI accelerator production. Scaling those packages, however, raises system-level challenges including heterogeneous integration, material compatibility, warpage control and sufficient capacity across the supply chain.

TSMC said at the OCP APAC Summit that its 5.5-reticle-size CoWoS package has entered mass production, with yields holding above 98% and reaching as high as 99%. The company plans to scale the technology to 14 times reticle size by 2029 while addressing integration and materials constraints. TSMC also identified ABF substrates as a potential next bottleneck after memory, highlighting shifting supply pressures as AI packages grow larger and more complex.

TSMC is advancing CoPoS, its next-generation panel-level advanced packaging technology, which uses square panels to accommodate more chips and improve both substrate-area utilization and AI chip packaging capacity. As demand for high-performance computing grows, CoPoS is seen as an important technology for extending the capacity expansion achieved with CoWoS. The shift is also reshaping supply-chain strategies among equipment makers in the United States, Japan and Taiwan.

The latest information shows that TSMC’s first CoPoS pilot line will be housed at the Longtan plant of its subsidiary VisEra Technologies. The initial batch of test equipment has arrived, with installation and process validation under way. TSMC has not disclosed the equipment investment or a full supplier list. Market estimates suggest that mass production, originally scheduled for a later date, could be brought forward to 2029, and equipment suppliers have begun competing for orders.