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ASE Develops Automated 310mm Panel-Level Packaging Line for AI and HPC Demand

2 reports · First detected 2026-05-27 · Last active 2026-05-27

Generative AI and high-performance computing chips are integrating more chiplets and high-bandwidth memory, driving demand for advanced packaging. ASE is replacing round wafers with rectangular panels in an effort to package more units per batch, reduce material waste and improve inter-die connectivity.

ASE has developed an automated production line for 310×310mm panel-level packaging, or PLP. It plans to begin mass production of its first large-format panel-level package by the end of 2026, while the fully automated line is expected to enter operation in the first half of 2027. Chief Operating Officer Tien Wu said future pricing would depend on market supply and demand as well as product yields. ASE has not disclosed the investment amount.

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ASE Unveils AI Packaging Roadmap Centered on VIPack and Silicon Photonics2026-08-03 · 1 reports · similarity 0.80

Generative AI is driving steep increases in computing and data-transfer demand, exposing constraints in power consumption, bandwidth and thermal management. ASE Technology Holding sees advanced packaging as central to sustaining AI hardware performance. Its strategy uses heterogeneous Chiplet integration to combine dies made with different processes and functions in a single package, improving system efficiency, interconnect density and design flexibility.

ASE’s latest advanced-packaging roadmap focuses on its VIPack platform, an automated panel-level packaging production line and silicon photonics, including co-packaged optics, or CPO. The technologies are intended to ease interconnect and power bottlenecks in high-performance AI systems. ASE also called for broader collaboration across the global semiconductor ecosystem, but did not disclose an investment amount, a production start date, customer commitments or a detailed commercialization timetable.

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